In part 1 of this three-part series, we looked at how the Ethernet began and some changes that have taken place since. Part 2 explores how FPGA technology has evolved to support FPGA-based network acceleration cards (NACs). This development has fostered the ability to design very flexible hardware platforms, supporting a broad range of existing and new use cases, all with an extended lifetime.
To begin this discussion, it is important to establish what to expect from a future-proof FPGA based NAC. An NAC hardware platform based on FPGA and designed to be future-proof should support:
- Different FPGA size configuration, providing the customer with the right cost/feature ratio options, enabling competitive product offerings
Ethernet link speeds and types available currently and in the near future, through attractive front port connectivity (see Figure 1)
FPGA-based NACs have traditionally implemented the so-called PHY devices in the data path between the FPGA and the Ethernet front port. The discreet silicon PHY device handles the physical layers of the Ethernet protocol stack.
The PHY device has usually been required to obtain the highest port rates because it added functionality not available in current FPGA technology. For other port rates, the PHY device represents an attractive compromise between cost and NAC features.
PHY devices are deployed for these primary reasons:
- Minimizing BOM cost
- FPGA transceiver speed limitations
- Logical resource constraints in the FPGA
For the above-referenced FPGA limitations, the PHY device neatly compensates, but it typically restricts the design in the number of supported Ethernet link speeds and potential types.
25G transceiver technology was introduced in the 28nm FPGA process node, but was only made available in a few high-end device options, available at a substantial cost, compared to the mainstream device options. For good reasons, besides the cost factor, the initial 100G FPGA-based NAC offerings deployed PHY devices implementing the required so-called gearbox functionality and optional error correction functionality. As with the previous PHY application, the gearbox PHY restricts these designs in the number of supported Ethernet link speeds to just 100G.
Now that Xilinx and Intel (formerly Altera) have introduced 20nm FPGA families, the FPGA technology is on par with the current and near-term future Ethernet link speeds, making the need for the PHY companion devices obsolete.
A PHY-less, FPGA-based NAC design poses, from a multi-link speed customer perspective, the following obvious benefits:
- Restriction of the required knowledge base to one platform
- Ability to source many different product variants with the same NAC part number
- Reducing the number of required hardware qualification resources
- Collecting volume on one or few NAC part numbers, pleasing logistics and pricing
- Ability to introduce multi-link speed product variants, eventually handling all major link speeds and types, on the same ports, through dynamic reconfiguration.
The third and final installment of this series will explore the related front port connectivity options that optimize the market value of the future-proof FPGA platform discussed above. It will cover physical form factor, supported link types and supported link speeds.